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VLSI Physical Design Manager/Designer (KW: APR, P&R)

Ambarella
Location 📍 Hsinchu City, Taiwan
Posted 📅 June 03, 2026
Work Type ⏰ Full-time

Position Overview

Role Description:
The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good.


Key responsibilities:
. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII).
. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications.
. Work closely with front-end design, DFT, and package teams to ensure design closure.
. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM).
. Analyze, optimize and resolve congestion, timing, ...

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Job Details

Employment Type
Full-time
📊
Category
Other-General
🏠
Work Arrangement
On-site
📍
Location
Hsinchu City, Taiwan