Position Overview:

We are seeking a highly skilled Design Verification Engineer with more than 5 years of experience, specializing in Display Interface protocols – specifically Display Port (DP/eDP) IP and subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, expertise in System Verilog (SV) programming & UVM Methodology, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.

Key Responsibilities:

• Develop and implement comprehensive verification plans for DP/eDP and DP Tunnelling over USB4 IP and Subsystems.
• Create and maintain testbenches using System Verilog and UVM methodology.
• Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
• Collaborate with designers and other cross-functional teams to understand design s...