Position Overview

We are seeking a highly skilled and experienced Design Verification Engineer with over 6 years of experience, specifically in UCIe IP and Subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.

Key Responsibilities:

Develop and execute verification plans for UCIe interfaces and chiplet interconnect IPs/subsystems.

Create and maintain testbenches (System Verilog/UVM or equivalent) for Subsystem and System-level verification testbenches.

Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.

Collaborate with design engineers to understand design specifications and requirements for IP and Subsystems.

Identify and resolve...