• Device model test structure generation and tape out preparation.
• Device pCell creation and FDK coordination.
• Device test structure data collection, analysis.
• Device manual bench for test key debug.

Capability

• Solid semiconductor device physics and analysis skill, experience on bipolar, power and RF device is a plus.
• Hands on experience on test key generation, familiar with commercial layout EDA tool, good script and coding skill is a plus.
• Good communication and team work skill.
• Self-motived and avid learner.

Qualification

• Bachelor's Degree and above, preferred in physics, EE.
• Working Experience: hands on experience on layout work.
• English Language level: good English oral and writing skill.