The VLSI Productivity and Infrastructure team supports 1000+ chip design engineers with strong automation and workflows necessary to create world-changing silicon. We are building the next generation of production semiconductor design-flow infrastructure: a control-plane-driven RTL-to-GDS platform that turns design intent, configuration, generated collateral, EDA tool execution, distributed jobs, validation checks, and shared project state into observable, repeatable implementation workflows.


This role is for a senior flow/platform engineer who can work across synthesis, physical design, timing, signoff, ECO, and hierarchical execution. If you can envision and evolve legacy Tcl/Make/Perl/YAML infrastructure into a cleaner, more structured system while keeping active projects running, this role is for you!


What You'll Be Doing:
+ Build and modernize production RTL-to-GDS flow infrastructure across synthesis, place-and-route, timing, signoff, ECO, and han...