Position Overview

We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely with RTL, Physical Design, DFT, CTS, and Signoff teams.

This role requires deep understanding of timing methodologies, advanced process nodes, low-power design considerations, and full-chip timing signoff flows for high-performance semiconductor products.