Technical Skills:
Well versed with the timing closure (STA), timing closure methodologies.
Pre/Post-layout constraint development to timing closure.
Handshake with the design team and develop functional/DFT constraints.
IP level constraint integration.
Multi-voltage/Switching aware corner definitions.
RC/C model selection understanding.
Abstraction expertise like Hyperscale/ILM/ETM.
RC Balancing and scaling analysis of full chip clock.
RC Balancing and scaling analysis of critical data paths.
Good automation skills in PERL, TCL and EDA tool-specific scripting.
chip and custom scripts for timing fixes
Qualification:
BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design.
Detailed knowledge of EDA tools and flows, Tempus/Primetime experience is must.
Experience – 7+ years.