As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state‑of‑the‑art verification methodologies in ever‑increasing design complexities, from UVM, C/C++ co‑simulation, system emulation to mixed‑mode simulation & formal verification. The goal is simple – to achieve zero‑defects with the best and smartest approach to the large verification space.
Requirements
Experience in UVM verification methodology.
Disciplined, quality‑minded, and highly driven for excellence.
Excellent team player and good communication skills.
MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results.
Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities.