Work with a cutting-edge DDR5/DDR6 product design team to simulate, analyze, and improve signal integrity and power integrity performance at the chip, package, and board levels.
Align SI/PI design targets with cross-functional teams and support trade-off decisions.
Support package, I/O buffer, and die/package PDN design.
Review SI/PI performance for die and package designs.
Create simulation benches for pre-layout and post-layout signal integrity and power integrity simulations.
Extract S-parameter, RLC, and transmission line models based on specific accuracy, bandwidth, and simulation runtime requirements.
Perform lab measurements to verify SI/PI performance and support troubleshooting/debug activities.
Qualifications
Master or PHD degree in Electrical Engineering or related field required.