Job Description
Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies. Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products. Job Requirements Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with 1 year or more experience Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation Static timing analysis, power and noise analysis and back-end verification across multiple projects. Proficient with backend design EDA tools, Synopsys ICC2 preferred Successfully track records...