At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits, investigating techniques to improve correlation of delay/SI analysis to SPICE, and modeling of nanometer circuit effects in delay/SI analysis.


The role involves designing, tuning, and innovating timing and graph algorithms operating on multi‑billion‑node timing graphs. These scale challenges require highly distributed, incremental, and parallel solutions, including opportunities to leverage GPU acceleration for performance‑critical workloads.

At advanced technology nodes, incorporating device variation and statistical modeling into the timing engine introduces add...