# **Welcome!**## .# **Job Details:**## Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels. You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.**Key Responsibilities*** Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff.* Architect and implement UVM environments (agents, drivers, monitors, sequencers, s...