Position Overview
Responsibilities
Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY moduleVerifying the IP integration with dedicated simulation environmentDevelopment and support test cases of different verification environmentsSupport worldwide customers on the IP integrationGet familiar to existing verification process, propose improvementsMaintain the traceability from the customer specification or the product specification to the architecture and verification results.Track and maintain verification productivity metricsReporting periodically on progress and difficultiesQualifications
Positive and self-driven achiever with:
Can Do AttitudeBachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplinesStrong analytical and problem-solving sk...