Probe Product Engineer – STPG Product Engineering

The Engineer owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM). The role defines probe coverage intent, establishes limits and guard‑bands grounded in silicon behavior, and drives yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

Key Responsibilities

• Probe Coverage Strategy & Ownership
  • Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
  • Define, release, and sustain probe test flows from first silicon through qualification and HV...