CADFEM APAC in Penang is looking for a skilled Design Verification Engineer to lead functional verification for semiconductor IPs and SoC platforms. This role involves maintaining verification environments with SystemVerilog and UVM, executing comprehensive test plans, and ensuring high-quality design signoff. The ideal candidate has a Bachelor’s or Master’s in Electronics/VLSI Engineering and over 4 years of experience in functional verification, coupled with strong debugging and analytical skills.
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