We are seeking a highly experienced and visionary Senior STA Leader to drive the static timing analysis strategy and execution for our advanced 3GHz+ CPU projects. In this role, you will lead the project, own the sign-off process, and collaborate with cross-functional teams to ensure first‑time‑right silicon. You will be responsible for hands‑on execution, developing methodologies, managing timing closure, and providing technical leadership across the organization.

• Oversee and ensure full‑chip and block‑level STA sign‑off using industry‑standard tools (PrimeTime, PrimeClosure), and establish sign‑off criteria and checklists.

• Define, develop, and implement advanced timing analysis methodologies and flows, including OCV/POCV, MMMC, hierarchical timing, and sign‑off automation.

• Guide the team in resolving complex timing clos...