Responsibilities:

• Define and realize digital functions on IPs, subsystem or IC level based on required specifications
• Perform design, verification and evaluation of digital functions
• Develop RTL using Verilog/SystemVerilog
• Support verification activities, including developing simple testbenches and debugging issues
• Participate in ASIC front-end design flow activities
• Analyze and debug design issues during development
• Collaborate with cross-functional teams
• Document design and related work

Requirements:

• BSEE or equivalent is required; MSEE is a plus
• Strong Verilog/SystemVerilog coding skills
• Knowledge of ASIC front-end design flows
• Experience in developing simple SystemVerilog/Verilog testbenches
• Around +2 years of working experience

Strongly desired:

• Knowledge of UVM is desirable
• Knowledge of C/C++, Matlab, Unix...