Position Overview
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Job Description:
Own end-to-end physical implementation for major IP blocks and/or full-chip designs, ensuring alignment with ADI’s Career Development Framework (Expertise, Autonomy & Scope, Business Impact).Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis)Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus).Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability.Automate design flows (e.g., hierarchical PNR, IO ring automation, Flash PG) to improve efficiency and quality; contribute to continuous flow enhancements.