Senior Design Verification Engineer

Job Description:

• SV / UVM Test bench development and test cases coding.
• Code and Functional coverage analysis and closure.
• Work with team for verification closure.
• Experience with python or any other scripting language is a plus.
• Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.

Experience: 3 to 8 Years.

Location: Bangalore.