MBR Partners is looking for a Senior ASIC Design Engineer to lead the end-to-end design of critical AI ASIC subsystems, focusing on efficiency and performance. The role requires a minimum of 7 years of experience in RTL design and ASIC development, with strong proficiency in Verilog/SystemVerilog. This position involves working closely with silicon architects and firmware teams.

Join a dynamic environment where your contributions will drive advancements in AI workloads.