Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis. <ul> <li>Experience in deciphering circuit behavior from schematics</li> <li>Familiarity with circuit characterization, timing libraries - files and formats, timing arcs</li> <li>Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.</li> <li>Hands-on experience with latch based designs and their timing requirements.</li> <li>Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.</li> <li>Familiarity with UVM is a plus</li> <li>Strong communication skills, with the ability to convey complex technical concepts to other design peers in...