RTL Design Engineer (SDC Constraints)
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We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.
Design and develop RTL (Verilog/System Verilog) for complex ASIC blocks and subsystems
Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)
Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure
Perform RTL quality checks, linting, and CDC analysis
Support timing debugging and constraint optimization across multiple design iterations
Participate in architecture discussions and design reviews
Ensure deliverables meet performance, power, and area (PPA) goals.
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7+ years of hands-on experience in RTL ASIC design
Strong and mandato...