Vivid Resourcing is looking for a Senior ASIC Design & Verification Engineer to join a fully remote, senior-level IC design team. The role involves developing RTL for digital ASIC blocks and participating in design reviews, with a strong focus on SystemVerilog and UVM-based verification. Candidates should have over 7 years of experience in ASIC design or verification, strong debugging skills, and familiarity with EDA tools. This freelance role supports a cutting-edge semiconductor development project.
#J-18808-Ljbffr