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Role

We are seeking a Principal Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out. You will lead methodologies and execution for DRC, LVS, PERC and related reliability checks, Floor-planning by working closely with Place-n-route, analog/mixed-signal, timing analysis and CAD teams to ensure first-time-right silicon.

Key Responsibilities

- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs.

- Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS.

- Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use.

- Define and enhance ...