At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for -

• Develop firmware for DDR5 PHY using microcontrollers

• Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.

• Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.

• Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.

• Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)

• Develop and Debug on Silicon bring-up boards.

Required Skills:

• Good Knowledge of DDR5 JEDEC spec, knowledge of diffe...