Position Overview
Job Description
We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes. This role is critical for ensuring design quality and convergence while meeting power, performance, and cost targets.
Job Description
Drive RTL-to-gate synthesis for complex multi-die MCU designs using industry-standard toolsOptimize for timing, power, and area while adhering to mature-node constraintsLead static timing analysis (STA) and timing closure activities across multiple corners and modesEnsure sign-off compliance for timing, power, and signal integrityWork closely with RTL, DFT, and physical design teams to resolve timing issuesOwn full chip constraints and design optimizations to achieve convergenceDefine and maintain synthesis and timing closure methodologies tailored for cost-sens...