Job Description•Lead the DV effort of a high-end CPU project.
• Architect and implement testbenches and their components using UVM-based methods.
• Lead the effort in building in-house BFMs, unit-level testbenches and stimulus.
• Work with the design team to create testplans. Implement checkers/assertions/coverages. Drive directed testcases and controlled random testcases based on the testplans.
• Work on the core-level verification using in-house testbenches. Triage bug reports, profile failure cases, check functional coverage and drive the effort of directed testcase generation.Requirement• Masters/Bachelor or above degree in electronic/electrical engineering, computer science, mathematics or physics.
• 10+ years of verification experiences
• Familiar with industry instruction set architects such as ARM, RISC-V and etc.
• Hands-on experience in the field of cache coherent fabric verification
• Solid experiences with SystemVerilog, UVM and etc.
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