As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr.DFT Engineers.
Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
Create test vectors or oversee their creation.
Collaborate with physical design team to close timing in DFT mode.
Sign-off DFT requirements are being met.
Work with testing team to bring-up test patterns on silicon.