Lead RTL design and implementation for AI chip SoC and subsystems.
Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.
Define microarchitecture, RTL partitioning, interfaces, and implementation plans.
Translate architecture and microarchitecture specifications into clean, reusable, synthesizable RTL.
Lead SoC/IP integration, bus/interconnect integration, and top-level connectivity.
Work with verification teams on test plans, simulation debug, coverage improvement, and design quality.
Work with physical design teams on synthesis, timing closure, area, power, congestion, and ECO issues.
Support FPGA/emulation, silicon bring-up, performance tuning, and post-silicon debugging.