Lead the Physical Design team at Astera Labs in Toronto, driving ASIC implementations for high-speed connectivity solutions. Oversee physical design execution from RTL to GDSII while mentoring engineers and ensuring quality.
Astera Labs is seeking an experienced Physical Design Engineering Manager to head a team responsible for implementing essential connectivity ASICs in the Signal Connectivity Group. Candidates should have strong expertise in physical design methodologies, specifically for complex SoCs at advanced nodes. This leadership role requires a combination of technical skills and team management to facilitate high-performance designs in today’s AI-driven landscape.
Key Responsibilities:
• Drive physical design execution from floorplan to GDSII
• Lead block and top-level design implementation
• Ensure timing closure and sign-off for complex designs
• Collaborate with diverse teams for design accuracy
• Mentor engineers and establish design best practices