Position Overview
The position requires Synthesis or/and Place and Route experience and CAD development skills to define and develop implementation tools and methodologies for PPA, Quality and shortening design cycle time, in close collaboration with Implementation and Physical Design teams.
This role’s responsibilities will include.
Improving the SoC Synthesis, Formal Verification, Place and Route methodologies for diverse Mobile, Compute, AI, IoT chips.Enabling new features from EDA tools or/and internal tools for PPA, turn-around time or enabling new advanced process nodes.Support design teams on CAD solutions, analyze their requests, and address their requests through ticket queues.Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.Setting up, augmenting, and maintaining a regression of complex Synthesis, P&R designs.Innovating on tool/flow techniques ...