We are looking for an experienced Physical Design Engineer with strong expertise in the complete RTL-to-GDSII flow and full-chip implementation. The ideal candidate should have hands-on experience in physical design flow development, timing closure, PPA optimization, and advanced node implementation.

Key Skills:

• Full-chip Physical Design
  
• RTL to GDSII Flow
  
• Floorplanning, CTS, Routing & Signoff
  
• STA and Physical Verification
  
• Flow Development & Automation
  
• Tcl/Perl/Python Scripting
  
• Advanced Node Experience Preferred