Job Description1. Serdes PMA IP architecture planning
2. Serdes PMA IP RTL coding
3. Serdes PMA IP front-end and back-end integration
4. Co-work with PCS and MAC design team and DV team for IP verification
5. Co-work with Analog design team for PHY co-simulation
6. Co-work with Algorithm team for algorithm implementation and bit-true verification

#LI-DC3
Requirement1. Good at RTL and digital circuit design
2. Familiar with front-end or back-end integration flow and related EDA tools
3. Knowledge of high speed interface standards such as Ethernet Serdes, PCIe, USB, HDMI, DP, MPHY, CPHY etc.
4. Experience in high speed Interface PHYD IP development
5. Experience in DSP based IP design, such as CDR, CTLE, FEC, FFE, FIR, IIR etc.