Job Description

CEG HIPD MYS is seeking a mixed‑signal design engineer to join our talented and vibrant team. You will be directly involved in delivering next‑generation DDR PHY designs for SOC application on Intel’s leading process node.

Key Responsibilities

• Develop a Mixed‑Signal Validation (MSV) testbench in accordance with the specified requirements.
• Own MSV for Custom Building Blocks (CBB) covering open‑loop functional checks, closed‑loop functional checks with RTL blocks, PHY level features, high volume manufacturing (HVM) features, and closed‑loop with Memory Reference Code (MRC) checks.
• Independently analyze the results based on specification documents and debug the root cause of failures.
• Participate in MSV result review and collaborate with designers.

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering.
• Education focus should include integrated c...