Position Overview: We are seeking a highly skilled Design Verification Engineer with more than 5 years of experience, specializing in HBM and DDR DRAM IP and subsystem verification, to join our innovative team. The ideal candidate will possess a strong background in verification methodologies, expertise in System Verilog programming, excellent problem-solving abilities, and the capacity to work collaboratively in a fast-paced environment.

Key Responsibilities:

1. Develop and implement comprehensive verification plans for HBM4/4e IP and Subsystem.
2. Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.
3. Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
4. Collaborate with design engineers to understand design specifications and requirements for IP and subsystems.
5. Identify and resolve...