Leadership: Lead a dynamic team of analog circuit designers in the development of PCIe 6.0 PHY IP.

Methodology Enhancement: Drive continuous improvement in design methodologies for architecture, circuits, and verification.

Performance Optimization: Ensure projects achieve an optimal performance-to-cost ratio.

Behavioral Modeling: Perform behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems.

Silicon Validation: Oversee silicon bring-up, characterization, and debugging processes.

Test Support: Provide support for factory test in DFT and vector generation to facilitate silicon validation.

Cross-Functional Collaboration: Collaborate with cross-functional teams to transition IP from schematics to mass production readi...