We are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team. The ideal candidate will have strong experience in RTL development, micro-architecture design, and SoC integration.

Location: Bangalore/Hyderabad

Experience: 8–15 Years

Key Responsibilities:

• Design and develop synthesizable RTL using Verilog/System Verilog

• Translate architecture specifications into micro-architecture and RTL implementation

• Develop high-performance and low-power digital design blocks

• Work closely with verification teams for functional validation and debug

• Perform design reviews and ensure coding quality and design guidelines

• Collaborate with physical design teams to meet timing, power, and area requirements

• Debug RTL issues and support silicon bring-up when required

Required Skills:

• Strong expertise in Verilog and System Verilog