At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview
Responsible for enabling Foundry PDK teams and Foundry Design Service teams to deploy signoff‑quality standard cell, IO, and memory libraries using Cadence Liberate Characterization Suite. This role focuses on library modeling methodology, characterization techfile development, and design‑ready reference flow enablement aligned with foundry signoff requirements.
Key Responsibilities – Foundry PDK Team Support

+ Support foundry PDK teams in development, validation, and maintenance of Liberate characterization techfiles for standard cell, IO, and memory libraries.

+ Collaborate with foundry teams to define SPICE corner, PVT, and RC assumptions used for library signoff.

+ Enable generation of signoff‑quality Liberty models (NLDM / CCS / CCSP) aligned with foundry requirements.

+ Support characterization of timing, power, leak...