Application Engineering Intern: Digital Verification & Simulation (VIP)

Cadence Design Systems Inc. seeks a motivated Application Engineering Intern to work in Belo Horizonte, Brazil. The Intern will be trained to become an expert in Digital Verification & Simulation methodologies within the System Verification Group – Technical Field Operations (TFO‑SVG). The role focuses on RTL‑level verification products, supporting customers with Cadence Verification IP solutions and related technologies.

Responsibilities

• Mentored by experienced colleagues and reporting to higher management.
• Provide technical support to customers and field personnel in RTL verification solutions focused on Cadence Verification IP and supporting technologies.
• Conduct root‑cause analysis and provide resolution to customer technical issues.
• Help develop and run test cases to verify problems, create workarounds when possible, and test and deliver R&D fixes....