Job Description1. High Speed digital design implementation
2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving
3. Signoff on design with mixed-signal interface
4. Design methodology and integration flow improvement

#LI-LL1Requirement1. Familiar with front-end or back-end implementation flow and related EDA tools
2. Familiar with CTS scheme and methodology, including clock tree analysis
3. Better to have chip integration, signoff and timing analysis experience
4. Better to have experience on handling mixed-signal interface
5. Better to have DFT/Scan domain knowledge and experience
6. Better to have physical implementation domain knowledge
7. Better to have Adaptative Voltage Scaling (AVS), PI/IR domain knowledge, including power analysis experience