Qualifications

: - Degree or Master in Electronic & Electrical Engineering or equivalent Requirements : - Strong understanding of digital design and VLSI fundamentals

- Expertise in DFT concepts: Scan architecture, ATPG, Fault models, Test compression

- Hands-on experience with industry-standard tools such as: Synopsys (DFT Compiler, TetraMAX/TestMAX), Cadence (Modus), Siemens EDA (Tessent)

- Experience in scripting (TCL, Python, or Perl) Job Descriptions : - Define and implement DFT architecture for SoCs and sub-systems

- Insert and verify Scan, MBIST , LBIST and Boundary Scan

- Perform scan insertion, ATPG (Automatic Test Pattern Generation), and fault simulation

- Analyze and improve test coverage (stuck-at, transition, path delay faults)

- Debug DFT and ATPG issues across simulation and silicon stages