Position Overview
Description
As a Design Verification Manager, you are expected to carry out the following responsibilities.
Be in-charge of a passionate verification team that is constantly pushing the limits Develop and deploy state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verificationConduct thorough test plan reviews systematically, and execute the plan on-time with high qualityAchieve zero-defects with the best and smartest approach to the large verification space.Requirements
Strong knowledge of SoC design principles, including IP block integration and system-level verificationExperience with test plan development, execution, and analysisFamiliarity with EDA tools and development flows for ASIC verificationHighly disciplined, quality-minded, and highly driven for excellence....