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⏰ Full-time

Design Verification Engineer

UST Malaysia
Location 📍 , penang, malaysia, Malaysia
Posted 📅 May 30, 2026
Work Type ⏰ Full-time

Position Overview

  • Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
  • Build verification environments and UVM/OVM testbenches based on chip requirements.
  • Work across RTL, power‑aware, and gate‑level verification.

Requirements

  • Bachelor’s degree (or higher) in Electrical/Electronic Engineering or related.
  • 3-8 years of hands‑on experience in digital IP verification using SV/UVM or similar methodologies.
  • Solid knowledge of ASIC verification concepts.
  • Bonus if you’ve dabbled in scripting (Perl/Python) or have database know‑how.
  • Willing to relocate and work in Penang, Malaysia

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Job Details

Employment Type
Full-time
📊
Category
Engineering
🏠
Work Arrangement
On-site
📍
Location
, penang, malaysia, Malaysia