About the Role We are seeking a skilled and motivated Design Verification (DV) Engineer with strong hands-on Ethernet verification experience to join our Datacenter Division . The ideal candidate will bring a solid foundation in SystemVerilog/UVM-based verification , a history of contributing to multiple successful tapeouts , and specific expertise in Ethernet protocol verification and UALink . This role offers the opportunity to work on cutting-edge datacenter networking silicon and directly contribute to next-generation Ethernet and accelerator interconnect IP development. Key Responsibilities Execute and contribute to the Design Verification effort for Ethernet IP blocks and accelerator interconnect interfaces targeted at high-performance datacenter applications Develop and maintain UVM-based testbench environments, including test cases, scoreboards, monitors, and functional coverage models Implement and verify protocol features with a focus on UAL and UEC functionality Write and re...