**Position:**
Design For Test Engineer (Einfochips Inc)

**Job Description:**

Job Description

**What You'll Be Doing:**

+ DFT implementation for 3nm and 5nm Networking chips, IP DFT work
+ RTL checks for scan-insertion compatibility using Synopsys Spyglass
+ Scan-Insertion using Tessent TestKompress
+ ATPG pattern generation:
+ Compressed and Uncompressed Mode
+ _Tools:_ Mentor Tessent, Cadence Modus & Synopsys Tetramax
+ Pattern Simulation:
+ Without timing, With timing for different corners
+ _Tools:_ VCS
+ Mismatch debug using _Verdi_
+ Scripting with Perl, Shell, TCL:
+ DAeRT - DFT flow enhancement/automation in project
+ Makefile enhancement using extended scripts and targets for flow enhancement
+ MBIST Insertion and Verification:
+ MBIST Insertion and Verification done on block on top
+ Silicon debug and bring-up done for block and top
+ IEEE 1149.1 JTAG Insertion and verification