Job Description1.Propose design verification plan and do the execution based on IP and system HW architecture/application
2.Develop design verification environment
3.Develop required verification methodology and adopt into project

#LI-YT1
Requirement1.Bachelor/Masters Degree in Electrical/Computer Engineering, RTL design experience
RTL verilog capability
2.Scripting capability (Ex: tcl, phython, perl ...etc.)
3.SystemVerilog, UVM capability
4.Formal verification capability is plus
C/C++ programming is a plus
5.Processor, Chip level architecture related design/verification experience is a plus