Job Description

Job Title: UVM Verification Engineer
Location: UK/Remote
Duration: 12 months' initial
Start Date: 1st July

A client based in in the UK is looking for a UVM verification Engineer, this will be for an initial 12 month contract with extensions. The role can be performed mainly remotely with up to 50% on-site ideally required.

The successful Verification engineer will be joining a team that is being newly formed within our client's offices and will help to expand on projects being worked, both new and existing within other teams. You will be involved in new and existing ASIC projects.

Skills:
- Strong background in ASIC Verification
- System Verilog/UVM
- SystemVerilog
- Verification Planning
- Used to working with complex ASIC and/or large FPGA designs

Knowledge of some of the following items would be a plus:
- C/C++
- Formal Verification