MediaTek, Bangalore Backend Integration Engineer (Staff/Senior Staff) KEY RESPONSIBILITIES: Utilize Synthesis tool variables and methodologies to extract the best PPA achievable. (Genus/Fusion Compiler) Analyze critical timing violation groups and congestion – solve them by finetune floorplan or placement constraints. DFT Insertion and debugging basic DFT DRC issues. Interact with Design teams & Physical design teams to get the best synthesis results. Experience in Logic Equivalence Checks Conformal LEC/Formality, Low power Checks (UPF/CLP). OR Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the timing checks at pre-layout/placement/pre-CTS/post-CTS/Route stages, debug skew/latency issues and achieve timing signoff. Ensuring timing correlation between PnR STA and timely feedback to PD team Driving SoC level timing Closure. Generating timing ECO using Tweaker/Prime Closure. PREFERRED EXPERIENCE: 5 years of experience in timing closure of hi...