Job Details

Job Description:

• Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
• Debug and resolve design and simulation issues, collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring‑up, and issue resolution.
• Ensure high design quality by following coding standards and maintaining proper technical documentation.

Qualifications

Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or S...