ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

What you'll be doing:
+ STA for hierarchical design.
+ Constraints creation and validation, timing budget.
+ Timing closure for both partition and full chip level.
+ Special timing closure, such as io, test, clock etc.
+ Synthesis, Netlist quality check, Formal Verification.
+ Implement chip partition and floorplan.
+ Function eco creation.
+ Develop and enhance entire timing closure f...